1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, specifically to a technology to form an isolation region to isolate a well region and a semiconductor element.
2. Description of the Related Art
In a semiconductor integrated circuit, an isolation region to electrically isolate a well region in which MOS transistors are formed and a semiconductor element such as a bipolar transistor from other semiconductor elements is conventionally formed by introducing impurities into a semiconductor substrate and thermally diffusing the impurities. Technologies for this kind of forming of the isolation region is disclosed in Japanese Patent Application Publication Nos. H09-97852 and H09-97853, for example.
When the impurities introduced into the semiconductor substrate are thermally diffused, however, there is a problem that the well region and the isolation region require a large horizontal pattern area that makes reducing a size of the semiconductor integrated circuit difficult because a lateral diffusion is caused along with a vertical diffusion (a diffusion toward a depth of the semiconductor substrate).